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3-94 pinouts ha-5020/883 (cerdip) top view ha-5020/883 (clcc) top view bal -in +in v- 1 2 3 4 8 7 6 5 disable v+ out bal + - 4 5 6 7 8 9101112 13 321 19 15 14 18 17 16 nc nc -in nc +in nc nc nc out v+ disable nc nc v- nc bal nc nc bal nc 20 + - ha-5020/883 100mhz current feedback video ampli?r with disable description the ha-5020/883 is a wide bandwidth, high slew rate ampli?r optimized for video applications and gains between 1 and 10. manufactured on intersils reduced feature complementary bipolar di process, this ampli?r uses cur- rent mode feedback to maintain higher bandwidth at a given gain than conventional voltage feedback ampli?rs. since it is a closed loop device, the ha-5020/883 offers better gain accuracy and lower distortion than open loop buffers. the ha-5020/883 features low differential gain and phase and will drive two double terminated 75 ? coax cables to video levels with low distortion. adding a gain ?tness performance of 0.1db makes this ampli?r ideal for demanding video applications. the bandwidth and slew rate of the ha-5020/ 883 are relatively independent of closed loop gain. the 105mhz unity gain bandwidth only decreases to 77mhz at a gain of 10. the ha-5020/883 used in place of a conventional op amp will yield a signi?ant improvement in the speed power product. to further reduce power, the ha-5020/883 has a disable function which signi?antly reduces supply current, while forcing the output to a true high impedance state. this allows the outputs of multiple ampli?rs to be wire-ord into multiplexer con?urations. the device also includes output short circuit protection and output offset voltage adjustment. the ha-5020/883 offers signi?ant enhancements over competing ampli?rs, such as the el2020. improvements include unity gain bandwidth, slew rate, video performance, lower supply current, and superior dc speci?ations. ordering information part number temperature range package ha7-5020/883 -55 o c to +125 o c 8 lead cerdip ha4-5020/883 -55 o c to +125 o c 20 lead ceramic lcc features this circuit is processed in accordance to mil-std- 883 and is fully conformant under the provisions of paragraph 1.2.1. wide unity gain bandwidth . . . . . . . . . . 105mhz (min) slew rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800v/ s output current . . . . . . . . . . . . . . . . . . . . . . 30ma (min) drives 3.5v into 75 ? differential gain . . . . . . . . . . . . . . . . . . . . . . . . . . 0.025% differential phase. . . . . . . . . . . . . . . . . . . . . . .0.025 deg low input noise voltage . . . . . . . . . . . . . . . . 4.5nv/ hz low supply current. . . . . . . . . . . . . . . . . . . 10ma (max) wide supply range . . . . . . . . . . . . . . . . . . . 5v to 15v output enable/disable high performance replacement for el2020/883 applications unity gain video/wideband buffer video gain block video distribution amp/coax cable driver flash a/d driver waveform generator output driver current to voltage converter; d/a output buffer radar systems imaging systems january 1996 spec number 511080-883 file number 3541.2 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | copyright intersil corporation 1999
3-95 speci?ations ha-5020/883 absolute maximum ratings thermal information (typical) voltage between v+ and v- terminals . . . . . . . . . . . . . . . . . . . . 36v differential input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8v voltage at either input terminal . . . . . . . . . . . . . . . . . . . . . . v+ to v- peak output current. . . . . . . . . . . . . . . . full short circuit protected junction temperature (t j ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175 o c storage temperature range . . . . . . . . . . . . . . . . . -65 o c to +150 o c esd rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . < 2000v lead temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . +300 o c thermal package characteristics ja jc cerdip package . . . . . . . . . . . . . . . . . . . . . . 115 o c/w 30 o c/w ceramic lcc package . . . . . . . . . . . . . . . . . 75 o c/w 23 o c/w package power dissipation limit at +75 o c for t j +175 o c cerdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.87w ceramic lcc package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.33w package power dissipation derating factor above +75 o c cerdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.7mw/ o c ceramic lcc package . . . . . . . . . . . . . . . . . . . . . . . . 13.3mw/ o c caution: stresses above those listed in ?bsolute maximum ratings?may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not im plied. operating conditions operating temperature range . . . . . . . . . . . . . . . . -55 o c to +125 o c operating supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 5v to 15v v incm 1/2(v+ - v-) r f = 1k ? r l 400 ? v disable = v+ or 0v table 1. dc electrical performance characteristics device tested at: supply voltage = 15v, r source = 0 ? , a vcl = +1, r f = 1k ? , r load = 400 ? , v out = 0v, v disable = v+, unless otherwise speci?d. parameters symbol conditions group a subgroup temperature limits units min max input offset voltage v io v cm = 0v 1 +25 o c-88mv 2, 3 +125 o c, -55 o c -10 10 mv common mode rejection ratio +cmrr ? v cm = +10v, v+ = 5v, v- = -25v 1 +25 o c60-db 2, 3 +125 o c, -55 o c50 - db -cmrr ? v cm = -10v, v+ = 25v, v- = -5v 1 +25 o c60-db 2, 3 +125 o c, -55 o c50 - db power supply rejection ratio +psrr ? v sup = 13.5v, v+ = 4.5v, v- = -15v; v+ = 18v, v- = -15v 1 +25 o c64-db 2, 3 +125 o c, -55 o c60 - db -psrr ? v sup = 13.5v, v+ = 15v, v- = -4.5v; v+ = 15v, v- = -18v 1 +25 o c64-db 2, 3 +125 o c, -55 o c60 - db non-inverting (+in) current i bp v cm = 0v 1 +25 o c-88 a 2, 3 +125 o c, -55 o c -20 20 a +in common mode rejection ibpcmp ? v cm = +10v, v+ = 5v, v- = -25v 1 +25 o c - 0.1 a/v 2, 3 +125 o c, -55 o c - 0.5 a/v ibpcmn ? v cm = -10v, v+ = 25v, v- = -5v 1 +25 o c - 0.1 a/v 2, 3 +125 o c, -55 o c - 0.5 a/v non-inverting (+in) input impedance +r in calculated 1/ibpcmp 1 +25 o c10-m ? 2, 3 +125 o c, -55 o c2 - m ? +in power supply rejection ibppsp ? v sup = 13.5v, v+ = 4.5v, v- = -15v; v+ = 18v, v- = -15v 1 +25 o c - 0.06 a/v 2, 3 +125 o c, -55 o c - 0.2 a/v ibppsn ? v sup = 13.5v, v+ = 15v, v- = -4.5v; v+ = 15v, v- = -18v 1 +25 o c - 0.06 a/v 2, 3 +125 o c, -55 o c - 0.2 a/v inverting input (-in) current i bn v cm = 0v 1 +25 o c -20 20 a 2, 3 +125 o c, -55 o c -50 50 a spec number 511080-883
3-96 speci?ations ha-5020/883 -in common mode rejection ibncmp ? v cm = +10v, v+ = 5v, v- = -25v 1 +25 o c - 0.4 a/v 2, 3 +125 o c, -55 o c - 0.5 a/v ibncmn ? v cm = -10v, v+ = 25v, v- = -5v 1 +25 o c - 0.4 a/v 2, 3 +125 o c, -55 o c - 0.5 a/v -in power supply rejection ibnpsp ? v sup = 13.5v, v+ = 4.5v, v- = -15v; v+ = 18v, v- = -15v 1 +25 o c - 0.2 a/v 2, 3 +125 o c, -55 o c - 0.5 a/v ibnpsn ? v sup = 13.5v, v+ = 15v, v- = -4.5v; v+ = 15v, v- = -18v 1 +25 o c - 0.2 a/v 2, 3 +125 o c, -55 o c - 0.5 a/v common mode range +cmr v+ = 5v, v- = -25v 1 +25 o c10-v 2, 3 +125 o c, -55 o c10 - v -cmr v+ = 25v, v- = -5v 1 +25 o c - -10 v 2, 3 +125 o c, -55 o c - -10 v transimpedance +a zol1 r l = 400 ? , v out = 0 to 10v 1 +25 o c1-m ? 2, 3 +125 o c, -55 o c1 - m ? -a zol1 r l = 400 ? , v out = 0 to -10v 1 +25 o c1-m ? 2, 3 +125 o c, -55 o c1 - m ? output voltage swing +v out v in = 12.8v 1, 2 +25 o c, +125 o c12 - v 3 -55 o c11-v -v out v in = -12.8v 1, 2 +25 o c, +125 o c - -12 v 3 -55 o c - -11 v +v out5 v+ = 5v, v- = -5v, v in = 3v 1 +25 o c2-v 2, 3 +125 o c, -55 o c2 - v -v out5 v+ = 5v, v- = -5v, v in = -3v 1 +25 o c - -2 v 2, 3 +125 o c, -55 o c - -2 v output current +i out note 1 1, 2 +25 o c, +125 o c30 - ma 3 -55 o c 27.5 - ma -i out note 1 1, 2 +25 o c, +125 o c - -30 ma 3 -55 o c - -27.5 ma short circuit output current +i sc r l = open, v in = 10v 1 +25 o c50-ma 2, 3 +125 o c, -55 o c50 - ma -i sc r l = open, v in = -10v 1 +25 o c - -50 ma 2, 3 +125 o c, -55 o c - -50 ma disabled output current +i leak v in = 0v, v out = +10v, r l = open, v dis = 0v 1 +25 o c-11 a 3 -55 o c-11 a v in = 2v 2 +125 o c-11 a -i leak v in = 0v, v out = -10v, r l = open, v dis = 0v 1 +25 o c-11 a 3 -55 o c-11 a v in = -2v 2 +125 o c-11 a table 1. dc electrical performance characteristics (continued) device tested at: supply voltage = 15v, r source = 0 ? , a vcl = +1, r f = 1k ? , r load = 400 ? , v out = 0v, v disable = v+, unless otherwise speci?d. parameters symbol conditions group a subgroup temperature limits units min max spec number 511080-883
3-97 speci?ations ha-5020/883 disable pin input current i logic v dis = 0v 1, 2 +25 o c, +125 o c-1 0 ma 3 -55 o c -1.5 0 ma minimum disable pin current to disable i dis note 2 1 +25 o c - 350 a 2, 3 +125 o c, -55 o c - 350 a maximum disable pin current to enable i en note 3 1 +25 o c20- a 2, 3 +125 o c, -55 o c20 - a quiescent power supply current i cc r l = 400 ? 1 +25 o c - 10 ma 2, 3 +125 o c, -55 o c - 10 ma i ee r l = 400 ? 1 +25 o c -10 - ma 2, 3 +125 o c, -55 o c -10 - ma disabled power supply current i ccdis r l = 400 ? , v dis = 0v 1 +25 o c - 5.6 ma 2, 3 +125 o c, -55 o c - 7.5 ma i eedis r l = 400 ? , v dis = 0v 1 +25 o c -5.6 - ma 2, 3 +125 o c, -55 o c -7.5 - ma offset voltage adjustment +v adj note 4 1 +25 o c30-mv 2, 3 +125 o c, -55 o c25 - mv -v adj note 4 1 +25 o c - -30 mv 2, 3 +125 o c, -55 o c - -25 mv notes: 1. guaranteed from v out test by i out = v out /400 ?. 2. this is the minimum current which must be sourced from the disable pin, to disable the output. the output is considered disabled when v out 10mv. conditions are: v in = 10v, r l = 100 ? . the test is performed by sourcing 350 a from the disable pin, and testing that the output decreases below the test limit (10mv). 3. this is the maximum current that can be sourced from the disable pin with the device remaining enabled. the device is considered disabled when the supply current decreases by at least 0.5ma. conditions are: r l = 400 ? . test is performed by sourcing 20 a from the disable pin, and testing that the supply current decreases by no more than the test limit (0.5ma). 4. the offset adjustment range is referred to the output. the inverting input current (-i bias ) can be adjusted with an external pot between pins 1 and 5, wiper connected to v+. since -i bias ?ws through r f , an adjustment of offset voltage results. the amount of offset adjustment is proportional to the value of r f . test conditions are: r l = open, 10k ? from pin 5 to v+, 1k ? from pin 1 to v+, for +v adj ; r l = open, 1k ? from pin 5 to v+, 10k ? from pin 1 to v+, for -v adj . table 2. ac electrical performance characteristics device tested at: supply voltage = 15v, r source = 50 ? , r load = 400 ? , c load 10pf, a vcl = +1v/v, unless otherwise speci?d. parameters symbol conditions group a subgroup temperature limits units min max slew rate +sr v in = -10v to +10v 4 +25 o c 600 - v/ s 5, 6 +125 o c, -55 o c 400 - v/ s -sr v in = +10v to -10v 4 +25 o c 600 - v/ s 5, 6 +125 o c, -55 o c 400 - v/ s table 1. dc electrical performance characteristics (continued) device tested at: supply voltage = 15v, r source = 0 ? , a vcl = +1, r f = 1k ? , r load = 400 ? , v out = 0v, v disable = v+, unless otherwise speci?d. parameters symbol conditions group a subgroup temperature limits units min max spec number 511080-883
3-98 speci?ations ha-5020/883 table 3. electrical performance characteristics device characterized at: supply voltage = 15v, r source = 50 ? , r load = 400 ? , r f = 1k ? , v disable = v+, c load 10pf, a vcl = +1v/v, unless otherwise speci?d. parameters symbol conditions notes temperature limits units min max -3db bandwidth bw 1 v o = 100mv rms , a v = +1 1 +25 o c 105 - mhz bw 10 v o = 100mv rms , a v = +10, r f = 360 ? , r l = open 1 +25 o c 77 - mhz gain flatness gf 5 v o = 100mv rms , f = 5mhz 1 +25 o c -0.075 +0.075 db gf 10 v o = 100mv rms , f = 10mhz 1 +25 o c -0.2 +0.2 db rise time t r v o = 0v to 1v, r l = 100 ? 1, 2 +25 o c - 3.7 ns fall time t f v o = 1v to 0v, r l = 100 ? 1, 3 +25 o c - 4.0 ns overshoot +ovs v o = 0v to 1v, r l = 100 ? 1 +25 o c - 18.0 % -ovs v o = 1v to 0v, r l = 100 ? 1 +25 o c - 16.6 % slew rate +sr 10 v o = -10v to 10v, a v = +10, r f = 360 ? , r l = open 1, 4 +25 o c 1070 - v/ s -sr 10 v o = 10v to -10v, a v = +10, r f = 360 ? , r l = open 1, 5 +25 o c 860 - v/ s disable time +t dis v o = 2v to 0v, 50% of v dis to 90% v o 1, 6 +25 o c - 3.13 s -t dis v o = -2v to 0v, 50% of v dis to 90% v o 1, 6 +25 o c - 2.44 s enable time +t en v o = 0v to 2v, 50% to 90% 1, 7 +25 o c - 1.45 s -t en v o = 0v to -2v, 50% to 90% 1, 7 +25 o c - 1.49 s notes: 1. parameters listed in table 3 are controlled via design or process parameters and are not directly tested at ?al production. these param- eters are lab characterized upon initial design release, or upon design changes. these parameters are guaranteed by characteriz ation based upon data from multiple production runs which re?ct lot to lot and within lot variation. 2. measured from 10% to 90% of the output waveform. 3. measured from 90% to 10% of the output waveform. 4. measured from 25% to 75% of the output waveform. 5. measured from 75% to 25% of the output waveform. 6. disable = +15v to 0v. measured from the 50% of disable to v out = 200mv. 7. disable = 0v to +15v. measured from the 50% of disable to v out = 1.8v. table 4. electrical test requirements mil-std-883 test requirements subgroups (see tables 1 and 2) interim electrical parameters (pre burn-in) 1 final electrical test parameters 1 (note 1), 2, 3, 4, 5, 6 group a test requirements 1, 2, 3, 4, 5, 6 groups c and d endpoints 1 note: 1. pda applies to subgroup 1 only. spec number 511080-883
3-99 ha-5020/883 die characteristics die dimensions: 65 x 60 x 19 mils 1 mils 1640 m x 1520 m x 483 m 25.4 m metallization: type: al, 1% cu thickness: 16k ? 2k ? worst case current density: 5.77 x 10 4 a/cm 2 at 30ma substrate potential (powered up): v- glassivation: type: nitride over silox silox thickness: 12k ? 2k ? nitride thickness: 3.5k ? 1k ? transistor count: 62 process: bipolar dielectric isolation metallization mask layout ha-5020/883 4 3 21 8 7 6 5 +in -in bal disable v+ out bal v- spec number 511080-883
3-100 ha-5020/883 test circuit (applies to table 1) test waveforms simplified test circuit for large and small signal pulse response (applies to tables 2 and 3) a v = +1 test circuit a v = +10 test circuit large signal waveform small signal waveform v+ icc 10 0.1 1k 10k 1k 10k k9 k10 bal. adj. 7 1 5 dut - + 2 3 4 8 1k (0.01%) 150pf 500 500 v in - + ha-5177 200pf 200k (0.1%) v z k7 v x x100 - + 0.1 v io = v x 100 +i bias = v z 200k 10 0.1 v- iee v disable 500 - + v y -i bias = v y 100k k3 k4 k1 1k 400 100 k12 v out note: all resistors = 1% ( ? ) all capacitors = 10% ( f) unless otherwise noted 0.1 x100 6 - + v in r s 50 ? c l r l v out v+ v disable r l 1k ? v- note: v s = 15v, a v = +1, c l 10pf r f = 1k ? , r s = 50 ? r l = 400 ? for large signal r l = 100 ? for small signal - + v in r s 50 ? r f v out v+ v disable v- 360 ? r g 40 ? note: v s = 15v, a v = +10, c l 10pf r f = 360 ? , r g = 40 ? r s = 50 ?, r l = open 75% 25% 75% 25% +10v -sr, -sr10 +10v +sr, +sr10 v out -10v -10v note: a v = +1: +sr, -sr a v = +10: +sr10, -sr10 90% 10% 90% 10% +1v tf, -ovs +1v tr, +ovs v out 0v 0v spec number 511080-883
3-101 ha-5020/883 simplified test circuit for enable/disable times positive enable/disable switching waveforms negative enable/disable switching waveforms test waveforms (continued) - + v in c l r l v out v+ v disable r f 1k ? v- note: v s = 15v, a v = +1, c l 10pf r f = 1k ? , r l = 400 ? 50% 50% +15v +15v v disable 0v 0v 10% +t dis +t en +2v +2v 0v 0v 90% v out 50% 50% +15v +15v v disable 0v 0v 90% -t dis -t en -2v -2v 0v 0v 10% v out spec number 511080-883
3-102 ha-5020/883 burn-in circuits ha7-5020/883 ceramic dip 1 2 3 4 8 7 6 5 + - v+ c1 d1 r3 r1 r2 d2 c2 v- spec number 511080-883
3-103 ha-5020/883 schematic diagram out +1 bal bal -in 5ibp 5ibn +in i ref v+ v disable v- spec number 511080-883
3-104 ha-5020/883 f8.3a mil-std-1835 gdip1-t8 (d-4, configuration a) 8 lead dual-in-line frit-seal ceramic package symbol inches millimeters notes min max min max a - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d - 0.405 - 10.29 5 e 0.220 0.310 5.59 7.87 5 e 0.100 bsc 2.54 bsc - ea 0.300 bsc 7.62 bsc - ea/2 0.150 bsc 3.81 bsc - l 0.125 0.200 3.18 5.08 - q 0.015 0.060 0.38 1.52 6 s1 0.005 - 0.13 - 7 s2 0.005 - 0.13 - - 90 o 105 o 90 o 105 o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - m - 0.0015 - 0.038 2 n8 88 packaging notes: 1. index area: a notch or a pin one identi?ation mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturers identi?ation shall not be used as a pin one identi?ation mark. 2. the maximum limits of lead dimensions b and c or m shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. 4. corner leads (1, n, n/2, and n/2+1) may be configured with a partial lead paddle. for this configuration dimension b3 replaces dimension b1. 5. this dimension allows for off-center lid, meniscus, and glass overrun. 6. dimension q shall be measured from the seating plane to the base plane. 7. measure dimension s1 at all four corners. 8. n is the maximum number of terminal positions. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch. 11. lead finish: type a. 12. materials: compliant to mil-m-38510. bbb c a - b s c q l a seating base d plane plane -d- -a- -c- -b- d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 a m s s e a ccc c a - b m d s s aaa c a - b m d s s spec number 511080-883
3-105 ha-5020/883 packaging (continued) d j x 45 o d3 b h x 45 o aa1 e l l3 e b3 b1 l1 d2 d1 e 1 e2 e1 l2 plane 2 plane 1 e3 b2 notes: 1. metallized castellations shall be connected to plane 1 terminals and extend toward plane 2 across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connection with the optional plane 2 terminals. 2. unless otherwise speci?d, a minimum clearance of 0.015 inch (0.381mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.) 3. symbol ??is the maximum number of terminals. symbols ?d and ?e?are the number of terminals along the sides of length ??and ?? respectively. 4. the required plane 1 terminals and optional plane 2 terminals shall be electrically connected. 5. the corner shape (square, notch, radius, etc.) may vary at the manufacturers option, from that shown on the drawing. 6. chip carriers shall be constructed of a minimum of two ceramic layers. 7. maximum limits allows for 0.007 inch solder thickness on pads. 8. lead finish: type a. 9. materials: compliant to mil-m-38510. j20.a mil-std-1835 cqcc1-n20 (c-2) 20 pad metal seal leadless ceramic chip carrier symbol inches millimeters notes min max min max a 0.060 0.100 1.52 2.54 6, 7 a1 0.050 0.088 1.27 2.23 7 b----4 b1 0.022 0.028 0.56 0.71 2, 4 b2 0.072 ref 1.83 ref - b3 0.006 0.022 0.15 0.56 - d 0.342 0.358 8.69 9.09 - d1 0.200 bsc 5.08 bsc - d2 0.100 bsc 2.54 bsc - d3 - 0.358 - 9.09 2 e 0.342 0.358 8.69 9.09 - e1 0.200 bsc 5.08 bsc - e2 0.100 bsc 2.54 bsc - e3 - 0.358 - 9.09 2 e 0.050 bsc 1.27 bsc - e1 0.015 - 0.38 - 2 h 0.040 ref 1.02 ref 5 j 0.020 ref 0.51 ref 5 l 0.045 0.055 1.14 1.40 - l1 0.045 0.055 1.14 1.40 - l2 0.075 0.095 1.90 2.41 - l3 0.003 0.015 0.08 0.38 - nd 5 5 3 ne 5 5 3 n20 203 spec number 511080-883
the information contained in this section has been developed through characterization by harris semiconductor and is for use as application and design information only. no guarantee is implied. 3-106 design information december 1999 typical performance curves v supply = 15v, a v = +1, r f = 1k ? , r l = 400 ? , t a = +25 o c, unless otherwise speci?d input noise vs frequency average of 18 units from 3 lots input offset voltage vs temperature absolute value average of 30 units from 3 lots +input bias current vs temperature average of 30 units from 3 lots -input bias current vs temperature absolute value average of 30 units from 3 lots frequency (hz) 10 100 1k 10k 100k 1 10 100 1 10 100 input noise voltage (nv hz) input noise current (pa hz) a v = +10 -input noise current input noise voltage +input noise current temperature ( o c) -60 -40 -20 0 20 40 60 80 100 120 140 offset voltage (mv) 2.5 2.0 1.5 1.0 0.5 0.0 v supply = 15v v supply = 4.5v v supply = 10v temperature ( o c) -60 -40 -20 0 20 40 60 80 100 120 140 0 -0.5 -1.0 -1.5 -2.0 -2.5 v supply = 15v v supply = 4.5v v supply = 10v bias current ( a) temperature ( o c) -60 -40 -20 0 20 40 60 80 100 120 140 bias current ( a) 2.0 1.8 1.6 1.4 1.2 1.0 v supply = 15v v supply = 4.5v v supply = 10v ha-5020 100mhz current feedback video ampli?r with disable spec number 511080-883
design information (continued) the information contained in this section has been developed through characterization by harris semiconductor and is for use as application and design information only. no guarantee is implied. 3-107 ha-5020 transimpedance vs temperature average of 30 units from 3 lots supply current vs supply voltage average of 30 units from 3 lots disable supply current vs supply voltage average of 30 units from 3 lots supply current vs disable input voltage disable mode feedthrough vs frequency disabled output leakage vs temperature average of 30 units from 3 lots typical performance curves v supply = 15v, a v = +1, r f = 1k ? , r l = 400 ? , t a = +25 o c, unless otherwise speci?d temperature ( o c) -60 -40 -20 0 20 40 60 80 100 120 140 open loop gain (m ? ) 6 5 4 3 2 1 v supply = 15v v supply = 4.5v v supply = 10v supply voltage ( v) 3 supply current (ma) 57 9111315 4 5 6 7 8 +125 o c +25 o c -55 o c supply voltage ( v) 3 supply current (ma) 57 9111315 0 4 5 6 7 +125 o c +25 o c -55 o c 1 2 3 disable = 0v disable input voltage (v) 13579111315 supply current (ma) 5 4 3 2 1 0 6 7 8 9 v supply = 15v v supply = 4.5v v supply = 10v 0 -10 -20 -30 -40 -50 -60 -70 -80 feedthrough (db) 024 68 1214 10 16 18 20 frequency (mhz) disable = 0v v in = 5vp-p r f = 750 ? temperature ( o c) -60 -40 -20 0 20 40 60 80 100 120 140 output leakage current ( a) 1.0 0.5 0 -0.5 -1.0 v out = +10v v out = -10v spec number 511080-883
design information (continued) the information contained in this section has been developed through characterization by harris semiconductor and is for use as application and design information only. no guarantee is implied. 3-108 ha-5020 enable/disable time vs output voltage average of 9 units from 3 lots non-inverting gain vs frequency inverting frequency response phase vs frequency bandwidth and gain peaking vs load resistance bandwidth and gain peaking vs feedback resistance typical performance curves v supply = 15v, a v = +1, r f = 1k ? , r l = 400 ? , t a = +25 o c, unless otherwise speci?d output voltage (v) -10 -8 -6 -4 -2 0 2 4 6 8 10 enable time ( s) 2.0 1.6 1.2 0.8 0.4 0.0 1.8 1.4 1.0 0.6 0.2 disable time ( s) 20 16 12 8 4 0 18 14 10 6 2 enable time disable time frequency (mhz) 0 24487296120 -7 -6 -5 -4 -3 -2 -1 0 +1 +2 +3 normalized gain (db) v out = 0.2vpp c l = 10pf a v = +1 a v = +2 a v = +6 a v = +10 frequency (mhz) 0 24487296120 -7 -6 -5 -4 -3 -2 -1 0 +1 +2 normalized gain (db) v out = 0.2vpp c l = 10pf a v = -1 a v = -2 a v = -6 a v = -10 r f = 750 ? -8 frequency (mhz) 0 24487296 120 -225 -180 -135 -90 -45 0 +45 a v = -1 a v = -2 a v = -6 a v = -10 -270 -135 -90 -45 +45 +90 +135 +180 -180 0 inverting phase (degrees) non-inverting phase (degrees) a v = +1 a v = +2 a v = +6 a v = +10 load resistance ( ? ) -3db bandwidth (mhz) gain peaking (db) 0 200 400 600 800 1000 60 70 80 90 100 110 0 1 2 3 4 5 gain peaking -3db bandwidth c l = 10pf v out = 0.2vp-p feedback resistor ( ? ) 700 900 1.1k 1.3k 1.5k 85 90 95 100 105 0 5 10 15 20 -3db bandwidth (mhz) gain peaking (db) gain peaking -3db bandwidth c l = 10pf v out = 0.2vp-p spec number 511080-883
design information (continued) the information contained in this section has been developed through characterization by harris semiconductor and is for use as application and design information only. no guarantee is implied. 3-109 ha-5020 bandwidth and gain peaking vs feedback resistance (a v = +2) bandwidth vs feedback resistance (a v = +10) rejection ratios vs temperature average of 30 units from 3 lots rejection ratios vs frequency output swing overhead vs temperature average of 30 units from 3 lots output voltage swing vs load resistance typical performance curves v supply = 15v, a v = +1, r f = 1k ? , r l = 400 ? , t a = +25 o c, unless otherwise speci?d feedback resistor ( ? ) 400 600 800 1.0k 1.2k 80 85 90 95 100 -3db bandwidth (mhz) gain peaking -3db bandwidth c l = 10pf v out = 0.2vp-p 0 5 10 15 20 gain peaking (db) feedback resistor ( ? ) 200 400 600 800 1000 40 50 60 70 80 -3db bandwidth (mhz) gain peaking = 0db c l = 10pf v out = 0.2vp-p 30 20 10 temperature ( o c) -60 -40 -20 0 20 40 60 80 100 120 140 rejection ratio (db) 75 70 65 60 55 psrr cmrr frequency (hz) 10k 100k 1m 10m rejection ratio (db) -50 -60 -70 -80 -90 +psrr cmrr -40 -30 -20 -10 0 -psrr a v = +10 temperature ( o c) output swing overhead ( v) 1.5 2.0 2.5 3.0 3.5 0 -20 -40 -60 80 100 120 140 60 40 20 v supply = 15v v supply = 4.5v v supply = 10v ( v supply ) - ( v out ) load resistance ( ? ) output voltage swing (vp-p) 10 15 20 25 30 10k 1k 100 10 5 0 v supply = 15v v supply = 4.5v v supply = 10v spec number 511080-883
design information (continued) the information contained in this section has been developed through characterization by harris semiconductor and is for use as application and design information only. no guarantee is implied. 3-110 ha-5020 short circuit current limit vs temperature small signal pulse response vertical scale: v in = 100mv/div.; v out = 100mv/div. horizontal scale: 20ns/div. large signal pulse response vertical scale: v in = 5v/div.; v out = 5v/div. horizontal scale: 50ns/div. propagation delay vs temperature average of 18 units from 3 lots typical performance curves v supply = 15v, a v = +1, r f = 1k ? , r l = 400 ? , t a = +25 o c, unless otherwise speci?d temperature ( o c) -60 -40 -20 0 20 40 60 80 100 120 140 40 50 60 70 80 90 100 short circuit current (ma) -isc +isc in out in out temperature ( o c) -60 -40 -20 0 20 40 60 80 100 120 140 propagation delay (ns) 7.0 6.5 6.0 5.5 5.0 r load = 100 ? v out = 1vp-p spec number 511080-883
design information (continued) the information contained in this section has been developed through characterization by harris semiconductor and is for use as application and design information only. no guarantee is implied. 3-111 ha-5020 propagation delay vs supply voltage average of 18 units from 3 lots small signal overshoot vs load resistance distortion vs frequency differential gain vs supply voltage average of 18 units from 3 lots differential phase vs supply voltage average of 18 units from 3 lots slew rate vs temperature average of 30 units from 3 lots typical performance curves v supply = 15v, a v = +1, r f = 1k ? , r l = 400 ? , t a = +25 o c, unless otherwise speci?d supply voltage ( v) 3579111315 5.0 6.0 7.0 8.0 9.0 10.0 11.0 propagation delay (ns) a v = +10 (r f = 383 ? ) r load = 100 ? v out = 1vp-p a v = +2 a v = +1 load resistance ( ? ) overshoot (%) 10 15 1000 800 600 0 5 0 400 200 v out = 100mvp-p, c l = 10pf v supply = 15v v supply = 5v a v = +2 a v = +1 a v = +1 a v = +2 frequency (hz) 1m 10m distortion (dbc) -50 -60 -70 -80 -90 hd2 v o = 2vp-p c l = 30pf hd3 hd3 (gen) hd2 (gen) 3 rd order imd 3 rd order imd (generator) supply voltage ( v) 3 5 7 9 11 13 15 differential gain (%) 0.01 0.02 0.03 0.04 0.05 0.06 0.07 r load = 1k r load = 150 ? r load = 75 ? frequency = 3.58mhz supply voltage ( v) 3 5 7 9 11 13 15 differential phase (degrees) 0.01 0.02 0.03 0.04 0.05 0.06 0.07 r load = 1k r load = 150 ? r load = 75 ? frequency = 3.58mhz 1200 1000 800 600 -60 slew rate (v/ s) -40 -20 0 20 40 60 80 100 120 140 + slew rate - slew rate v out = 20vp-p temperature ( o c) spec number 511080-883
3-112 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/o r speci?ations at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of p atents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see web site http://www.intersil.com sales of?e headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (321) 724-7000 fax: (321) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil (taiwan) ltd. taiwan limited 7f-6, no. 101 fu hsing north road taipei, taiwan republic of china tel: (886) 2 2716 9310 fax: (886) 2 2715 3029 ha-5020 typical performance characteristics device characterized at: supply voltage = 15v, r f = 1k ? , a v = +1v/v, r l = 400 ? , c l 10pf, v disable = v+, unless otherwise speci?d parameters conditions temperature typical design limit units input offset voltage v cm = 0v +25 o c 2 table 1 mv average offset voltage drift versus temperature full 10 15 v/ o c positive input bias current v cm = 0v +25 o c 3 table 1 a negative input bias current v cm = 0v +25 o c 12 table 1 a input common mode range full 12 table 1 v offset voltage adjustment see note 4, table 1 full 40 table 1 mv output voltage swing v in = 12.8 +25 o c to +125 o c 12.7 table 1 v v in = 12.8 -55 o c to 0 o c 11.8 table 1 v output current implied by v out /400 ? +25 o c 31.7 table 1 ma output short circuit current v in = 10v, v out = 0v +25 o c 65 table 1 ma quiescent supply current r l = open full 7.5 table 1 ma supply current, disabled r l = open, v dis = 0v full 5.0 table 1 ma slew rate v in = 20vp-p +25 o c 800 table 2 v/ s overshoot v o = 1vp-p, r l = 100 ? +25 o c 7 table 3 % input noise voltage f = 1khz +25 o c 4.5 8 positive input noise current f = 1khz +25 o c 2.5 4 negative input noise current f = 1khz +25 o c2540 differential gain r l = 150 ? , ntc-7 composite +25 o c 0.025 0.05 % differential phase r l = 150 ? , ntc-7 composite +25 o c 0.025 0.05 degrees nv hz ? pa hz ? pa hz ? spec number 511080-883

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